Feature
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Metrology ROI| thinfilmmfg.com
Feature
Index
Metrology ROI |
For most fabs, metrology is an insurance policy. Just as insurance protects against external risks, like fires and earthquakes, metrology protects against process risks, like defects and parametric yield loss. No fab wants to spend more on insurance, or metrology, than necessary. Yet new processes and increasing process complexity make process risks more difficult to evaluate and control. Fabs need more information, and often get it by investing in metrology. Metrology and inspection account for 15% or more of capital purchases, according to Kevin Monahan, KLA-Tencor VP of technology. Within 10 years, metrology should reach 20% of capital purchases, and some fabs are already spending even more.
Unfortunately, sources of yield loss are increasing quickly, too. In a study for SEMATECH, Robert Leachman and Neil Berglund of UC Berkeley found that mature process yields have declined steadily since the 500 nm (0.5 micron) node. Though the SEMATECH study only had access to data through the 180 nm node, most observers expect the trend to continue as features shrink and processes become more complex. Without effective metrology, yields would almost certainly be even worse. Still, it's clear that simply measuring more sites or more electrical parameters will not necessarily improve yield enough to justify the additional cost. Process integration issues, rather than particles and other defects, are responsible for an increasing share of yield loss. Traditional metrology strategies, focused as they are on single process modules, may not supply the information needed to combat new sources of yield loss. The ideal metrology strategy would give the fab all the information it needs to solve problems quickly, while minimizing the "insurance premium" paid.
Like any process equipment, metrology tools carry purchase costs, operating costs, and costs associated with the cleanroom space they occupy. They also bring costs associated with lost production: while a wafer is at the metrology tool, it is not moving through the circuit fabrication process. Dedicated test wafers use production capacity that might otherwise be used for device wafers. According to Robert Wright, SEMATECH's factory simulation project manager, the organization's generic logic process flow model attributes about 40% of wafer moves to metrology. These wafer moves potentially represent substantial lost production time. The number of wafer moves due to metrology has been roughly constant for several technology nodes, Wright said, even as the value of each wafer has increased.
The most obvious route to reduced metrology cost is to reduce the cost of each individual measurement, and increasing throughput is one way to do that. For example, according to Neal Sullivan, VP of technology at Soluris, the company's CD-SEM achieves a move-acquire-move time of only about 3.5 seconds. A larger image field can also capture several measurements at each image location.
Increasing throughput is only possible to a point. While an imaging technique can capture a larger image field, other kinds of measurements depend on optical, acoustic, and other spectra. More sensitive spectroscopy tends to require smaller measurement spots, and often longer acquisition times as well.
Nor does increasing throughput necessarily reduce cost. Wright observed that
metrology is never the bottleneck in fab operations. In most fabs, the bottleneck
is lithography, which must expose every field on every wafer. Metrology and
inspection tools typically sample only some sites on some wafers. Metrology
thus has little or no impact on total fab throughput. On the other hand, faster
measurements reduce the required metrology capacity, saving both capital expense
and cleanroom space. Alternatively, as Philips AMS chief technologist Michael
Gostein observed, faster metrology equipment allows the fab to make more measurements
at constant cost. More complete sampling can reveal patterns that might otherwise
be invisible. For example, center-to-edge variation is very common in CMP. Routinely
sampling sites all along the wafer diameter allows much better understanding
and control of this variation. In DRAM manufacturing, the shape and dimensions
of the capacitor trench can vary with location on the wafer. Philips AMS' high
speed thin film infrared metrology supports rapid, accurate measurements of
the trench etch profile.
In photography, image clarity depends in part on the grain size of the photosensitive emulsion (or the pixel size, in digital photography). Larger grains lead to a fuzzier picture. Similarly, a high density of accurate measurements can more clearly resolve the process behavior. Granularity is especially important as fabs try to implement wafer level control. Lot-to-lot control is based on mean values over a lot; while wafer-to-wafer control depends on wafer-level mean values and therefore requires greater information density.
Another way to measure the cost effectiveness of metrology is by the value derived from each measurement. If a measurement supports significant yield improvement, it will easily justify its cost. Measurements on production wafers, for example, often provide better information with less disruption of normal manufacturing. Many processes behave differently depending on the circuit pattern. Both etch and CMP remove material at different rates in dense and isolated features. Resolution-enhanced photomasks seek to exploit pattern-dependent optical effects to produce the desired resist image. Only measurements of patterned wafers can accurately characterize pattern dependencies.
A single measurement can also add more value by providing several different pieces of information. For example, Rudolph's MetaPulse technology uses laser-generated acoustic pulses to measure the thickness of layers in a film stack. As the acoustic pulse travels through the stack, its propagation characteristics change depending on the material, allowing thickness measurements. However, Christopher Morath, Rudolph's director of marketing, explained that the raw data collected by the system actually measures the change in optical reflectivity with time. It turns out that the acoustic pulse creates strain as it passes, changing the dielectric constant of the material. Similarly, the thermal layer that accompanies the pulse affects the band structure of the film. By extracting thermal reflectance and piezoreflectance information from the raw data, fabs can measure interface characteristics like adhesion and contamination.
As Monahan pointed out, extracting several kinds of information from a single measurement reduces the noise inherent in the data. For example, Monahan explained that scatterometry can measure film thickness, CD, and feature profile simultaneously. All three measurements come from the same location under the same measurement conditions. If a measurement requires multiple tools, then the need to reposition the wafer and reacquire the measurement site will inevitably degrade the precision of the measurement. When the error budget for a feature is only a few nanometers, even low levels of measurement noise can be important.
In many cases, Tom Sonderman, director of automated precision manufacturing at AMD observed, advanced processes may require more sophisticated measurement tools, but not necessarily more of them. Though CD information might be collected by scatterometry rather than by a CD-SEM, the need for CD information itself has not changed. Even though transistor metrology is becoming substantially more difficult, interconnects account for most of the increase in metrology purchases. While a 65 nm node integrated circuit still has only one transistor layer, Wright said, it might have as many as ten metal layers. Each of these requires CD, overlay, and etch metrology, as well as defect inspection, film thickness measurements, and so on.
Along with more precise, more sophisticated measurements, Sonderman said, fabs need to make better use of the data they have. When most defects could be traced to a single process step, traditional statistical process control could maintain appropriate control limits. CD and overlay measurements tracked lithography performance, etch depth and uniformity measurements tracked etch performance, and so on. As features shrink, though, processes are increasingly interdependent. For example, the location and shape of a contact or via depends on both the lithography process's ability to transfer the mask pattern to resist, and the etch process's ability to transfer the resist pattern to the wafer. Malformed contacts and unlanded vias can occur if any of the constituent processes is out of specification, Yet defects can also occur when the processes are individually within specification, but their interaction falls outside the combined process window. For example, a smallish CD combined with a relatively large overlay error might create an unlanded via, while the same CD and a smaller overlay error might create a functional device.
Traditional SPC assumes a worst case scenario: good vias can only exist if all individual process specifications are met. In actual practice, however, a small via CD alone does not necessarily create a defect. The defect arises from the interactions among the processes used to create the via. Thus, effective process control must ensure that the via module as a whole falls within the desired process window, but must avoid overspecifying the individual unit processes. This approach is likely to be more manufacturable than worst-case controls, requiring less downtime and creating fewer bad wafers.
Actually implementing more flexible controls requires more sophisticated data analysis and management tools. First, the fab must understand the relationship between lithography, etch, and finished via performance as measured by electrical test. Second, the fab's scheduling and dispatch system must be able to consider the expected performance of each process tool, and manage wafers and recipes accordingly. Finally, the individual process tools must receive correct instructions for processing each lot, and must respond to recipe changes in a predictable and repeatable way.
Collectively, this approach is known as advanced process control. Sonderman emphasized that it does not necessarily require additional metrology. In the example discussed here, the etch, CD, and overlay measurements already exist. Instead of more metrology, APC requires better analysis of existing data, and better sharing of that data within the fab.
By reducing the cost of each individual measurement, extracting more information from it, and making better use of the information, fabs can control the costs of metrology for advanced processes. Still, Sonderman said, even further improvement is possible. He observed that the fab's goal is not to meet specific overlay or CD targets, or even to achieve a via defect target, but rather to maximize total ROI by delivering the most chips at the lowest cost. The fab's overall metrology strategy should conform to that overarching goal.
The purpose of metrology is to prevent unpleasant surprises and insure against unknown risks. Most process tools have consistent performance from one wafer to the next, and vary in a predictable manner over time. While substantial sampling might be needed to characterize the tool variation in the first place, much less is needed to confirm that it is in fact behaving according to the prediction. The most cost effective measurement of all is the one that never takes place.
This approach to metrology holds that oversampling is as bad as undersampling. No measurement is perfect, and each introduces uncertainty. Both the measurement location and the reported value represent a range, not a precise number. If the sample is too large relative to the amount of expected variation, the noise inherent in the measurements themselves can swamp the actual signal. At AMD, Sonderman said, adaptive sampling has allowed the company to reduce the number of measurements by 50%, without loss of process control.
As process technology continues to advance, fab engineers need more sophisticated measurements for insight into more complex problems. Transmission electron microscopy, once dismissed as too slow and difficult for production use, may be the only tool accurate enough for analysis of advanced gate stacks. Porous dielectrics, high aspect ratio features, and even vertical gate transistors will demand more from metrology and inspection tools. Cost effective manufacturing depends on the fab's ability to perform these measurements quickly, to use the data effectively, and to perform only those measurements that actually contribute to fab performance.
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