Feature
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Thermal processes | thinfilmmfg.com
Feature
Index
Thermal processes |
In textbooks, transistors are always perfect. Sharp lines define smooth interfaces between junctions, dielectrics, and contacts. As feature sizes shrink, the differences between idealized transistors in textbooks and real integrated circuits become more pronounced. Dielectrics allow leakage current. Junction edges blur. Contacts consume the underlying silicon.
In real circuits, thermal processes help define the interfaces between regions and layers. They supply essential energy for oxidation, dopant activation, and other steps, but can also drive diffusion and defect formation. Process engineers face a constant tradeoff between minimizing unwanted atomic movement and supplying enough energy to make the process work.
Gate dielectric formation is one of the first, and one of the most important, thermal process steps. The gate dielectric completes the capacitor formed between the gate electrode and the channel. Its dielectric strength determines both the operating voltage and the reliability of the device. In ideal transistors, the gate dielectric is a perfect barrier to electron flow. Real dielectrics, however, can disrupt this ideal picture in three ways, all of which get worse as dielectric layers become thinner.
First, the dielectric can fail outright. If the voltage across the material exceeds its dielectric strength, charge jumps across the gap and a hard breakdown occurs. After a hard breakdown event, the capacitor is shorted and the transistor no longer functions. Hard breakdown is nothing new, but thinner dielectrics are more susceptible.
As gate dielectrics get thinner, though, a more insidious soft breakdown problem is emerging. The physical mechanisms of soft breakdown are not yet clearly understood. The prevailing hypothesis, K. L. Pey (Nanyang Technological University, Singapore) and other researchers explained at the December 2002 IEEE Electron Device Meeting (IEDM; San Francisco), relies on charge traps created in the dielectric by electrical stress. If the traps are close enough together, electrons can tunnel between them. A string of such traps can form a conduction path allowing electrons to cross the gate dielectric. Leakage current increases after a soft breakdown event, but the transistor still functions.
Even in the absence of soft breakdown, leakage current due to direct tunneling is a serious problem for very thin oxide dielectrics. Leakage current increases the overall power consumption of the device and erodes the distinction between the "on" and "off" current allowed by the device. Once leakage current becomes comparable to the on-state current, the device fails. Low power devices are more vulnerable to this type of failure because the signal strength in such devices is lower to begin with. Low power devices are also less tolerant of leakage current-induced power consumption.
Both leakage current and soft breakdown get worse as the gate dielectric gets thinner. Unfortunately, the gate dielectric thickness must scale with the channel length.
Table: Gate length, dielectric thickness, and dielectric leakage requirements.
| Requirement | 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007 |
| MPU printed gate length (nm) | 90 | 75 | 65 | 53 | 45 | 40 | 35 |
| MPU physical gate length (nm) | 65 | 53 | 45 | 37 | 32 | 28 | 25 |
| MPU Equivalent physical oxide thickness (nm) | 1.3-1.6 | 1.2-1.5 | 1.1-1.4 | 0.9-1.4 | 0.8-1.3 | 0.7-1.2 | 0.6-1.1 |
| Gate dielectric leakage at 100°C (nA/µm) High-performance | 10 | 30 | 70 | 100 | 300 | 700 | 1000 |
| Physical gate length low power (nm) | 90 | 80 | 65 | 53 | 45 | 37 | 32 |
| Equivalent physical oxide thickness for low operating power (nm) | 2.0-2.4 | 1.8-2.2 | 1.6-2.0 | 1.4-1.8 | 1.2-1.6 | 1.1-1.5 | 1.0-1.4 |
| Gate dielectric leakage (pA/µm) LOP | 100 | 100 | 100 | 300 | 300 | 300 | 700 |
| Equivalent physical oxide thickness for low standby power (nm) | 2.4-2.8 | 2.2-2.6 | 2.0-2.4 | 1.8-2.2 | 1.6-2.0 | 1.4-1.8 | 1.2-1.6 |
| Gate dielectric leakage (pA/µm) LSTP | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Leakage current depends on the dielectric strength. A material with a higher dielectric constant (k; SiO2's is about 4) will allow less leakage current at the same physical thickness. Process engineers are considering a wide range of alternative materials, from the mundane, like nitrided SiO2 (k ~ 5-10), to the exotic, like HfO2 (k~10-20). SiO2 is chemically stable, can tolerate high temperatures, is compatible with the rest of the process, and serves as a good barrier to dopant diffusion from the gate electrode. No alternative material has demonstrated that it can meet all of these requirements. The ITRS committee does not expect high-k dielectric materials other than oxynitrides to be ready for manufacturing until 2006. Originally, researchers anticipated that an SiO2 replacement would be needed for the 90 nm node, which is now entering early production.
The delay has important implications for thermal processing systems. Just as the delayed introduction of low-k dielectrics has forced designers to work around high interconnect capacitance, the lack of an alternative forces circuit designers to rely on SiO2 gate dielectrics, despite their unsatisfactory leakage current and questionable reliability. Successful integration of gate oxides less than 2.0 nm thick requires precise control of the manufacturing process. Surface roughness and oxide thickness tolerances are now on the order of an atomic layer or less.
Most fabs rely on furnaces for the stable temperature and gas flow ultrathin oxide deposition needs. Furnace oxidation exposes all of the wafers in a large batch to the same process conditions, while rapid thermal oxidation is prone to fluctuations in lamp intensity and other variables. On the other hand, Gary Miner, director of technical marketing at Applied Materials, explained that furnace oxidation is difficult to scale to oxide thicknesses less than 2.0 nm. At high temperatures, oxidation happens too quickly, while low furnace temperatures degrade oxide quality.
These limits, and the introduction of new dielectric materials, are creating opportunities for RTP systems. Casey Bennett at FEI explained that the properties of nitrided gate oxides depend on both the concentration and bonding state of nitrogen. Fabs, Bennett said, "have to understand the behavior of nitrogen in the oxide. Is it covalent, or substitutional, or both?" Rare earth oxides like HfO2 tend to form non-stoichiometric compounds whose properties depend on oxygen concentration. These compounds may also require additional layers to prevent diffusion from the dielectric into the channel, or from the gate electrode into the dielectric. Such careful control of composition and abrupt changes in process chemistry are easier to achieve in single-wafer systems. The gas flow characteristics of a furnace allow only gradual changes in composition. According to Miner, "Customers are using in situ steam generation for rapid thermal oxidation from the 130 nm node on. We expect a substantial amount of gate oxide will be formed in RTP chambers."
On the other hand, according to Brian Desmarais, director of marketing for RTP and implant at Axcelis Technologies, "A few customers see oxide formation returning to furnaces for these very complex emerging oxide structures. Long cycle time oxide formations are done better in furnaces. The choice of systems is very process and customer dependent."
Junction activation is the second major thermal step in transistor formation. Because thermal budget control is so important to junction performance, much recent innovation in thermal processing has focused on this step.
The thermal budget includes all of the high temperature steps seen by the transistors, but it is most often discussed in the context of junction formation and activation. A MOSFET depends on two p-n junctions: between the source and the channel and between the channel and the drain. In real transistors, the source and drain regions face several often conflicting constraints. First, the sheet resistance of these regions should be as low as possible. Low resistance improves device speed and reduces power consumption. Sheet resistance depends on carrier concentration. Increasing the ion implant dose reduces sheet resistance.
Second, the junction depth must scale with the other transistor dimensions. Shallower junctions consume less power and allow faster switching. The energy of the implanted ions defines the initial junction depth. Shallow junctions require low energy implants.
Table: Contact and junction thickness and resistivity requirements
| Requirement | 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007 |
| MPU printed gate length (nm) | 90 | 75 | 65 | 53 | 45 | 40 | 35 |
| MPU physical gate length (nm) | 65 | 53 | 45 | 37 | 32 | 28 | 25 |
| Drain extension Xj (nm) | 27-45 | 22-36 | 19-31 | 15-25 | 13-22 | 12-19 | 10-17 |
| Maximum Drain extension sheet resistance (PMOS) (W/sq) | 400 | 460 | 550 | 660 | 770 | 830 | 760 |
| Maximum Drain extension sheet resistance (NMOS) (W/sq) | 190 | 220 | 260 | 310 | 360 | 390 | 360 |
| Contact Xj (nm) | 48-95 | 39-78 | 33-66 | 27-45 | 24-47 | 21-42 | 18-37 |
| Maximum silicon consumption (nm) | 23-46 | 19-38 | 16-32 | 13-26 | 11-23 | 10-20 | 9-18 |
| Silicide Thickness (nm) | 35.8 | 29.2 | 24.8 | 20.4 | 17.6 | 15.4 | 13.8 |
| Contact Silicide sheet Rs (W/sq) | 4.2 | 5.1 | 6.1 | 7.4 | 8.5 | 9.7 | 10.9 |
| Contact maximum resistivity (W-cm2 x 10-7) | 4.10 | 3.20 | 2.70 | 2.10 | 1.80 | 1.60 | 1.10 |
If the trajectory of implanted ions is aligned with a crystal direction, ions will encounter few obstructing atoms and can travel long distances. Manufacturers often implant helium or another inert gas in order to pre-amorphize the crystal structure and prevent channeling of the dopant implant.
To contribute free carriers to the semiconductor, the dopant ions must be "activated," or placed in substitutional locations in the crystal lattice. Both the pre-amorphization implant, if there is one, and the dopant implant disrupt the lattice structure. An annealing step is essential to restore the lattice and give dopant ions enough activation energy. Unfortunately, dopant activation requires a temperature of 1000°C or more, raising the risk of diffusion.
Diffusion both increases the junction depth and reduces the doping concentration. The higher the dopant concentration, the greater the driving force for diffusion. The diffusion rate depends on the temperature: the more mobile the atoms are, the more easily they can move. The more time the wafer spends at elevated temperature, the further diffusing dopants will travel. As a result, an extended time at a moderate temperature allows more diffusion than a short time at a higher temperature. The thermal budget for diffusion thus refers to the area under the junction's time vs. temperature history.
Dopant activation, in contrast, depends only on temperature. It requires very high temperatures, but they need not be maintained for more than a few seconds. An ideal process has ramp up and cool down times as short as possible, with almost all the thermal exposure occurring at the target temperature.
The large batches typical of a conventional furnace represent a large thermal mass. Neither the wafers nor the furnace itself can change temperatures quickly. Rapid thermal processing systems depend on halogen lamps, a much smaller thermal mass, and process only one wafer at a time.
Though lamp-based RTP systems have largely displaced furnaces for dopant activation, they present new problems of their own. Lamp heating is purely radiative. As such, the temperature reached by the wafer depends on its optical absorption, which in turn depends on the surface composition. Optical pyrometry, used for instantaneous temperature measurements, likewise depends on the optical emissivity of both the wafer and the process chamber, both of which are difficult to determine in advance.
Lamp-based RTP systems use several dozen lamps to achieve consistent heating over the full wafer area. Like any light bulb, those lamps eventually burn out. Fluctuations in the lamp output lead to fluctuations in the temperature and temperature uniformity. Moreover, lamp systems rarely reach steady-state operation, spending most of their time either ramping up or cooling down. It's difficult to avoid overshooting the final temperature or the process time. Furnaces, in contrast, remain at a stable, consistent temperature most of the time.
The Axcelis Summit 300 XT system attempts to minimize thermal budget while retaining the advantages of a furnace. The process chamber, a SiC bell jar, uses resistive heating elements to maintain a constant temperature gradient. The wafer is pushed into the furnace to the point corresponding to the desired temperature. Though the system's thermal budget is greater than that of some lamp-based RTP systems, Desmarais explained that the system is able to deliver more consistent results.
Smaller transistors will require even sharper spike anneals. Even lamp-based RTP systems aren't fast enough. Just as a light bulb remains hot after the power turns off, so do the halogen lamps in an RTP system. According to Miner, future devices will require ramp rates orders of magnitude faster than halogen lamps can achieve.
Two technologies that can achieve near instantaneous heating are arc lamps and lasers. Arc lights strike a spark between two electrodes. With no filament, they turn off as soon as the power source does. Laser thermal processing melts and refreezes the surface of the wafer in a matter of nanoseconds, activating the dopants but without allowing time for diffusion.
As ramp rates increase, achieving temperature uniformity becomes more difficult. Different materials heat at different rates. Standing structures heat and cool more quickly than the wafer bulk. These variations, a matter of a few tenths of a degree or a few fractions of a second, are unimportant for conventional thermal processes. They are already beginning to affect RTP systems, though, and will become even more important at the extreme ramp rates expected of arc light or laser-based systems.
The junction and the gate capacitor define the transistor, but a single transistor can accomplish very little. Most processes use metal silicide contacts to link the source, drain, and gate with the rest of the circuit. The silicide process deposits a metal on the doped region, then reacts the metal with the underlying silicon at elevated temperature. Titanium silicide has given way to cobalt silicide in recent years because CoSi2 offers lower contact resistance.
Silicon consumed in the contact formation reaction is no longer part of the junction. Most transistor specifications allow the silicide reaction to consume no more than half the total junction depth, a goal which becomes more difficult to achieve with ultrashallow junctions. The simplest way to reduce silicon consumption is to form a compound which pairs only one silicon atom with each metal atom. Nickel silicide, a monosilicide, is being considered to replace CoSi2. Unfortunately, NiSi forms only at temperatures above 300°C, while NiSi2 forms at temperatures above 350°C. Such low temperatures lie at the low end of the range accessible to lamp-based RTP systems. The necessary temperature control, Desmarais said, "essentially requires the lamps to operate on a dimmer switch in the bottom 5% of its range. From a systems perspective, that's very difficult to do consistently."
Process engineers are also considering alternatives like selective deposition of silicon in the contact regions. Such a sacrificial silicon layer could prevent consumption of the junction region altogether. At the IEDM meeting, researchers involved in Intel's 90 nm technology development reported that silicon germanium, used to increase carrier mobility in some advanced transistor designs, impedes cobalt silicide formation. SiGe transistors are likely to require a silicon buffer layer or a switch to nickel silicide contacts. Laser annealing can control the depth of the silicide reaction, serving as an alternative or adjunct to a silicon buffer layer.
So far, manufacturers have been able to use the same thermal systems for both contact formation and dopant activation. The requirements of the two steps are diverging, however. Dopant activation requires high temperature and very short spike anneals. NiSi contact formation requires low temperatures. These divergent requirements may force manufacturers to adopt a third furnace type, somewhere in between the high temperatures and fast ramp of RTP and the steady state batch processing of a conventional furnace. Meanwhile, few thermal processing systems can meet all of the requirements of the many proposed alternative gate dielectric schemes.
Whether contact and junction furnaces diverge or not, whether gate dielectrics are best manufactured in RTP systems or furnaces, it is clear that thermal processes are facing stringent, and sometimes conflicting, requirements. Any given device structure can be achieved by several different process routes. Which one a particular fab chooses may depend on cost and compatibility with an existing tool set, as well as on process capability.
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