Feature
Articles
Semicon West 2003| thinfilmmfg.com
Feature
Articles
Semicon West 2003 |
25 July 2003
As they do every year, attendees at last week's Semicon West swapped rumors and speculated about the outlook for the industry. Yet, after three years of consistently bad news, the usual self-fueling energy of the show has been replaced by something like grim determination. "Business is bad, and we don't see it getting good again soon, but there's nothing we can do about it except manage our businesses as well as we can." In previous years, I've seen optimism and elation, or else misery and depression. This year, I saw realism. Cautious optimism, yes, as fab utilization continues to rise and chipmakers begin to recover pricing power. But optimism tempered by the memory of three years of false hopes.
In spite of the positive signs, no one anticipates a strong upturn in the second half of 2003. At the same time, people seem reasonably sure that a bottom has been reached. There are rumblings of big fab projects in the works, but nothing anyone is willing to attach names or dates to.
The mid-year edition of the SEMI Capital Equipment Consensus Forecast expects sales to increase about 4% this year from the $19.8 billion posted in 2002. The forecast calls for 24% growth in 2004, and 18% in 2005. For 2003, North America and Taiwan will continue to shrink, with the fastest growth occuring in Japan and the Rest of World region (mainly mainland China). The wafer process segment will shrink in 2003, offset by strong test assembly and packaging growth.
At the show, people seemed to be beginning to confront the idea that this isn't just another downturn and may represent a qualitative change in the way the industry works. The gloomiest think that we may be seeing the demise of semiconductor equipment manufacturing, as no applications could possibly drive the kind of growth the industry needs. A more optimistic view is that the world is only starting to see what ubiquitous computing and ubiquitous connectivity can do, and once software catches up to the hardware we'll see another great boom, comparable to the adoption of PCs. This view anticipates the return of the Internet economy, but grounded in reality rather than hype.
If this downturn represents a qualitative change in the way the industry works, then there are a few things companies should keep in mind going forward:
While the show floor was quiet all week, most of the technical sessions were packed. Companies expect that advanced technology will continue to offer competitive advantage, as it has throughout the industry's history.
At the KLA-Tencor Yield Management Seminar, Carlos Mazuré from Soitec talked about metrology requirements for SOI and other engineered substrates. According to Mazuré, yield issues in SOI substrates raise new metrology needs. Composition, interfaces, strain, and lattice parameter all need to be measured and monitored. The 65 nm node is likely to see SiGe on insulator and ultrathin SOI. In this environment, metrology needs to become proactive not reactive, Mazuré said. It's necessary to understand materials behavior rather than merely fixing defects. Metrology needs to develop in parallel with technology advances. For example, ellipsometry measurements typically have a 20Å machine-to-machine variation, but the target thickness for SOI is only 150Å. Therefore metrology limits Soitec's ability to improve the Unibond process. It's necessary to understand the impact of the base wafer on the final properties of the material and its process behavior. Mazuré argued for a four-way partnership among IDMs, OEMs, materials companies, and metrology suppliers.
Also at the show, Soitec and ASM International demonstrated 200-mm strained silicon on insulator wafers. The material, targeted for the 65-nm node, uses a SiGe template for growth of silicon. Soitec is also partnering with IMEC and Umicore to develop germanium on insulator wafers.
IMEC announced a program to explore a Ge-based technology for high-performance CMOS transistors compatible with silicon baseline CMOS. Ge has recently regained significant interest within the semiconductor industry, the research consortium said, due to its high mobility and compatibility with high-k materials. These features could make Ge CMOS devices ideally suited for high-performance, low power circuits with improved performance compared to advanced strained Si layers. The Ge CMOS devices program seeks to demonstrate the feasibility of fabricating Ge devices in a state-of-the-art Si production line.
IMEC is also investigating the use of strained Si to improve carrier mobility. The research covers strained Si formation on top of SRB (strain relaxed buffer) layers, silicide formation, shallow junctions and extensions, compatibility issues, advanced strain characterization and device demonstration.
Immersion lithography drew a lot of attention at the show, partly because of a Sematech workshop on the technology held the previous week. Burn Lin of TSMC, speaking at the KLA-Tencor Yield Management Seminar, explained that immersion lithography gives a 132 nm effective wavelength at 193 nm actual wavelength. This allows either a larger numerical aperture or smaller physical lens. At 193 nm the immersion liquid is water. The effective wavelength is the wavelength in air divided by the refractive index of the fluid.
Immersion also doubles the available depth of field, Lin said, because there's no refraction at the air interface with photoresist. Scattering and reflection at immersion interfaces appear to be harmless. Lin thinks 193 nm lithography can be used in the 32 nm technology node with immersion lithography and aggressive resolution enhancement. The key research issues concern the effects of fluid on the lens and wafer surfaces. Lin also thinks the remaining issues for 157 nm lithography are intractable. In particular, calcium fluoride quality and availability, nitrogen purging, and photoresist are all very difficult problems at 157 nm. He expects electron beam lithography and direct write lithography have potential for contact layers and small volume runs.
According to Paul van Attekum at ASML, immersion lithography is a relatively minor modification. Stepper designs need to change a few lens elements and change the wafer stage to accommodate the immersion fluid. He expects the second generation of immersion lithography will bring numerical apertures greater than one. Such large numerical apertures require new lens designs with very large angles and very big lenses. Polarization effects are serious at such high numerical apertures. It's not yet clear whether the polarization effects outweigh the advantages of immersion.
Van Attekum expects that immersion lithography (at 193 nm, with water as the immersion liquid) will have a feasibility proof or disproof by the end of this year. The Sematech workshop on immersion lithography found no obvious technical roadblocks. Potential issues like bubbles and resist compatibility appear to be either less significant than anticipated or solvable. Among alternatives, most people are highly skeptical of EUV, despite Intel's very public support. EUV faces much more significant engineering and infrastructure issues than 157 nm lithography. (On the subject of EUV, the Sputtered Films technology recently acquired by Tegal is, according to Jim McKibben, well-suited to advanced masks for both DUV and EUV.) At the same time, customer support of 157 nm lithography is relatively weak, and is not necessarily accompanied by purchase commitments.
While resist contamination by the fab ambient has been a problem for several technology generations, the 157 nm resists are themselves a threat to the stepper environment and the lens. It's not clear exactly how much outgassing occurs or how contamination levels correlate to resist performance, in part because the concentrations are near current detectability limits. Extraction Systems is working on technology to improve detection of part per trillion level contaminants.
The combination of lithography issues, low-k dielectric integration, and design difficulties in the sub-100 nm world is making it hard for second-tier companies to move forward, particularly since the market does not seem to be screaming for the capabilities that sub-100 nm chips can provide. The gap between early adopters and volume production is widening, making it difficult for equipment suppliers to achieve an adequate return on their investments. Something's got to give, and the answer will probably be a slower pace of technology introductions.
Yet some of the most promising applications may not require sub-100 nm technology. RFID tags for very low cost applications are starting to become technologically feasible. As Tegal's Jim McKibben pointed out, a trillion of anything is a huge amount of silicon, even if the individual devices are the size of a fingernail clipping. FeRAM is especially interesting for these devices.
Even as the leading edge moves on, companies are still struggling to assimilate "old" technologies like copper interconnects. Even at 130 nm, copper yields are reputedly less than 50%. Anyone who says they have a process figured out when yield is less than 50% is lying. It's therefore likely that people who claim to have 90-nm processes "in place" are also lying, since 90-nm is much harder than 130-nm. Lots of opportunities still exist for people who can offer significant yield improvements.
ATMI's Tom Baum said the company in expects copper to exceed tungsten as a fraction of total metallization by 2005, aluminum by 2008. Copper process control, which depends on electroplating bath chemistry, is likely to remain challenging for some time to come.
Applied Materials' new SlimCell ECP system features a new platform that, the company claims, dramatically increases the technical capability, repeatability and production-worthiness of the electroplating process. The system links a small-volume plating cell to its own small chemical tank, which is completely replaced after processing a set number of wafers. This method reduces chemical cost per wafer by more than 2x over conventional large bath systems. The individual-cell approach also supports multi-step processing with specific chemistries to optimize the gap-fill and planarization portions of the plating sequence.
At Novellus, Tim Archer says the company is working with chemistry suppliers Shipley and Enthone to develop copper chemistry that will allow a larger process window. For 65 nm features, copper electrofill remains a big issue, as are defects, CMP integration, and productivity.
Novellus's Vector system allows deposition of all dielectrics in one physical machine, whether low-k, silicon nitride or silicon carbide. So far, no company yet dominates low-k dielectric, Archer said. ASM International, the leader, now has 35% of the market for dielectric constants less than 3.0.
Axcelis announced a new Paradigm system, focused on high productivity chain implants. The company says the medium-energy system is capable of almost all well and channel implants.
ATMI, which also had the best giveaway of the show --a 64MB flash keychain drive--has introduced a new version of their SDS low pressure implant gas source. According to Jim Mayer, SDS3 delivers 2-4x more gas in the same volume. The company also offers a vacuum-actuated cylinder for safer delivery of high-pressure gases. Because it's safer, the cylinder can hold more gas at higher pressure. The company claims it saves more than $134,000 per year per implanter. Separately, ATMI alleged Praxair is infringing VAC patents, seeking damages and an injunction.
There wasn't as much actual wafer processing equipment on the floor this year as usual. Many small exhibitors who haven't been able to get space in previous years did this year. It appears that the exhibit waitlist has cleared out as established exhibitors have cut back or eliminated their space.
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