Just back from the IEDM in San Francisco. As usual, it was probably the best run and most useful conference I attended this year. It will take me a little while to process everything I learned, but here's the thirty second summary:

Strained silicon was the hot topic. Intel is in production at 90nm with a process that combines overlayers with SiGe source and drain to apply uniaxial strain to NMOS and PMOS transistors. IBM and AMD jointly announced their own approach, using compressive and tensile nitride overlayers. But how well will local strain scale to smaller feature sizes, and how compatible is strained silicon with other needed performance enhancements?

Metal gates and hafnium gate dielectrics were a close second. The problem is that silicided gates like NiSi are relatively easy to integrate with hafnium oxide, but lead to Fermi level pinning and the associated loss of threshold voltage control. Current thinking is that high performance devices are likely to turn to metal gates to avoid poly depletion, while tolerating the high leakage of oxynitride dielectrics. Low power devices need the low leakage of hafnium oxide, and are likely willing to tolerate Fermi level pinning in order to get it.